1. Field of the Invention
The present invention relates to an information processing apparatus (or a data processing device) having an internal debug support mechanism or debug support function. In particular, the present invention relates to an information processing apparatus (or a data processing device) which can provide debug information for a branch instruction and data related to a memory access instruction or to a stack push instruction to an external device such as an external debug unit and the like. Further, the information processing apparatus of the present invention can efficiently provide information for debugging. In particular, a higher priority level is given to a branch instruction executed by an instruction execution device in the information processing apparatus so that it can be transmitted to an external debug unit without increasing the buffer size of a debugging FIFO (First in First Out) buffer. Moreover, the information processing apparatus of the present invention is capable of judging what kind of instruction or data is overflowed from a FIFO buffer for debugging.
2. Description of the Prior Art
When a programmer develops an application program executed on a conventional information processing apparatus, it is very important for the programmer to know trace data of operations performed by the information processing apparatus in a debugging stage.
So, it is very important to transmit the trace data of execution performed by the information processing apparatus as debug data and to transmit and store the trace delta to and in an external debug device for debugging.
It would be ideal to store trace data items for all operations performed by the information processing apparatus in the external debug device. However, this is not practical because the number of the trace data items of all operations performed by the information processing apparatus are too large. In order to overcome the problem in the conventional information processing apparatus described above, only the data related to a branch instruction executed by the information processing apparatus is transmitted to an external debug device and stored as a branch data. By getting this branch data, a programmer can trace the execution or operation flow of the information processing apparatus for debugging.
FIG. 1 is a configuration diagram of a conventional information processing apparatus 10. The conventional information processing apparatus 10 comprises only one FIFO (First in First Out) buffer 2 for storing debug data transmitted from an instruction execution unit 1. The FIFO buffer (FB) 2 comprises four buffers representing four stages. When the four buffers in the. FIFO buffer 2 are filled with debug data items, the data transmitted from the instruction execution unit 1 cannot be stored in the FIFO buffer 1.
Under this condition, we will now explain how the debug data is transmitted from the FIFO buffer 2 to an external debug unit (EDU) 5.
When a branch instruction execution signal JP or a memory access execution signal RW changes from an inactive state (Low level, for example) to an active state (High level, for example), debug data on a debug information output bus DATA is stored in one of the buffers in the FB 2. At the same time, the debug data is stored with a code indicating whether the debug data is for a branch instruction or a memory access instruction.
Next, the debug data stored in the FIFO buffer 2 is transmitted to the external debug unit 5.
The debug data which is read out first from the FIFO buffer 2 is the debug data which is the oldest debug data.
The external debug unit (EDU) 5 knows an internal state of the information processing apparatus 10 during debugging operation by interpolating debug data items such as a branch source address and memory access data related to a branch instruction and a memory access (read/write) data from the external memory 3 transmitted through a debug information bus (DINF).
In the debugging operation for an application program (APRG) by the external debug unit 5, the instruction execution trace data is one of the important data for debugging. In other words, a programmer can find bugs in an application program by observing an active state of the application program by using the instruction execution trace data.
If the external debug unit (EDU) 5 can get an application program (APRG) stored in the external memory 3 and this application program is not changed, a programmer can analyze bugs in the application program by tracing back execution of branch instructions. Therefore, the most important information or data for debugging is information about where a branch instruction has been executed in the application program (APRG).
We will now explain the debug operation for a conventional information processing apparatus which transmits only a branch source address related to a branch instruction and the problem caused by the conventional information processing apparatus.
Next, we are explaining concretely how the execution trace or operation trace of the information processing apparatus (IPA) 10 can be known debug data related to branch operations with reference to FIGS. 2A to 2C.
FIG. 2A shows an execution flow of the information processing apparatus 10 executing the application program APRG. In FIG. 2A, solid lines with arrows indicate the execution flow.
At time T1, when the information processing apparatus 10 executes a subroutine call instruction CALI which is a branch instruction, the information processing apparatus 10 transmits a first debug data DINF1 including a branch source address ORGPC1 to the external debug unit 5 through a DINF line.
Next, at time T2, when the information processing apparatus 10 executes a subroutine return instruction RETI which is also a branch instruction, the information processing apparatus 10 transmits a second debug data DINF2 including a branch source address ORGPC2 to the external debug unit 5 through the DINF line. FIG. 2B shows the first and second debug data items DINF1 and DINF2.
The external debug unit (EDU) 5 for debugging connected to the information processing apparatus 10 receives the debug data items DINF1 and DINF2, and analyzes them based on a debugging software. We will explain the debugging operation for the debugging data items DINF1 and DINF2 with reference to FIG. 2C.
At first, as clearly shown in FIG. 2C, it can be observed that the branch instruction CALI is executed at the branch address ORGPC1 after the information processing apparatus 10 has executed instructions until the branch source address ORGPC1. In this case, the instruction indicated by the branch source address ORGPC1 in the application program APRG is a subroutine call instruction CALI. Therefore it can be understood that the branch instruction is a subroutine call instruction at the branch address ORGPC1. A target address of this branch operation is known by decoding the subroutine call instruction CALI. In the specification, the target address of the branch operation will be referred to as a branch target address DSTPC.
Following the above operation, by analyzing the second debug data DINF2, the information processing apparatus 10 executes instructions between the branch target address DSTPC and the branch source address ORGPC2 in order. Further, the information processing apparatus 10 executes again a branch instruction at the branch source address ORGPC2.
The content of the branch source address ORGPC2 in the application program, in this case, is a subroutine return instruction RETI.
In general, when the subroutine return instruction RETI indicated by the address ORGPC2 is executed, the operation flow returns to an address which is immediately following the subroutine call instruction indicated by the address ORGPC1. Therefore, the branch target address of the subroutine return instruction RETI is an address next to the branch source address ORGPC1 in which subroutine call instruction is stored. This target address is referred to as a branch source address ORGPC1+.
Thus, when the information processing apparatus 10 transmits the debug data items DINF such as DINF1, DINF2 to the external debug unit 5, the external debug unit 5 analyzes these debug data items and reconstructs the operation trace of the information processing apparatus 10 by using the debug data items and the application program APRG based on the debug program.
Although the external debut unit 5 can analyze operation trace of the conventional information processing apparatus 10 by the debugging method described above, it cannot observe information related to data used in execution of the application program APRG. In this case, there is not enough debug data for debugging. This is a problem.
In order to overcome the above problem caused by the conventional information apparatus, another debug operation is performed by a conventional information processing apparatus. In this case, the conventional information processing apparatus generates and transmits not only a branch source address about a branch instruction, but also data related by a memory access instruction such as read-out/write-in instructions to an external debug unit. In this conventional information processing apparatus, the instruction execution unit 1 transmits debug data items such as the branch source address about he branch instruction and the data about the memory access instruction to the FIFO buffer 2 by activating a branch instruction execution signal JP and a memory access execution signal RW, as shown in FIG. 1.
However, all debug data items are stored without checking the priority degree or the priority level of each of the debug data items for debugging in the conventional information processing apparatus 10. In the configuration of the information processing apparatus shown in FIG. 1, debug data related to an important branch instruction is overflowed.
For example, we assume a case where the four buffers in the FIFO buffer 2 are empty. In this case, at first, a first branch instruction is executed by the information processing apparatus 10, and then four memory access instructions accessing the external memory 3 are executed in order. At the time when the fourth memory access instruction is executed, if the external debug unit 5 does not read out the contents in two buffers in the FIFO buffer 2, there is no empty buffer in the FIFO buffer 2. In this case, when a second branch instruction is executed, the branch information relating to this second branch instruction is overflowed. The branch source address about the second branch instruction is a very important debug data for debugging. Therefore the debugging operation cannot be carried out. This is a problem.
As described above in detail, in the conventional information processing apparatus has following two problems (1) and (2).
(1) In the first conventional case, there is no debug data related to memory access instructions in an application program executed by the conventional information apparatus. Information for debugging is not enough.
(2) In the conventional second case, all of debug data items related to a branch instruction and a memory access instruction are stored without checking a priority level of each of the instructions executed by the conventional information processing apparatus. In this case, debug data about a branch instruction which is the most important debug data is often overflowed from a FIFO buffer.